275 search results - page 29 / 55 » Design for Verification of SystemC Transaction Level Models |
110
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CODES
2006
IEEE
15 years 8 months ago
2006
IEEE
This paper presents a methodology to combine Transaction Level Modeling and System/Network co-simulation for the design of networked embedded systems. As a result, a new design di...
100
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HPCC
2009
Springer
15 years 6 months ago
2009
Springer
Compared with lock-based synchronization techniques, Software Transactional Memory (STM) can significantly improve the programmability of multithreaded applications. Existing res...
143
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SIGSOFT
2003
ACM
16 years 2 months ago
2003
ACM
Automated finite-state verification techniques have matured considerably in the past several years, but state-space explosion remains an obstacle to their use. Theoretical lower b...
119
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CODES
2008
IEEE
15 years 2 months ago
2008
IEEE
With power becoming a major constraint for multi-processor embedded systems, it is becoming important for designers to characterize and model processor power dissipation. It is cr...
104
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DSD
2009
IEEE
15 years 8 months ago
2009
IEEE
— In this paper, we present a novel framework for the automated generation of Network-on-Chips (NoC) architectures, that enables architecture exploration and optimization. The au...