275 search results - page 35 / 55 » Design for Verification of SystemC Transaction Level Models |
MTV
2005
IEEE
15 years 3 months ago
2005
IEEE
The increasing complexity and size of system level design models introduces a difficult challenge for validating them. Hence, in most industries, design validation takes a large p...
ICCAD
2009
IEEE
14 years 7 months ago
2009
IEEE
Boolean satisfiability (SAT) based methods have traditionally been popular for formally verifying properties for digital circuits. We present a novel methodology for formulating a...
ATAL
2008
Springer
14 years 11 months ago
2008
Springer
Business contracts tend to be complex. In current practice, contracts are often designed by hand and adopted by their participants after, at best, a manual analysis. This paper mo...
LCTRTS
2010
Springer
15 years 4 months ago
2010
Springer
With increasingly more complex Multi-Processor Systems on Chip (MPSoC) and shortening time-to- market projections, Transaction Level Modeling and Platform Aware Design are seen as...
VLSID
2002
IEEE
15 years 10 months ago
2002
IEEE
Satisfiability of complex word-level formulas often arises as a problem in formal verification of hardware designs described at the register transfer level (RTL). Even though most...