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» Design for Verification of SystemC Transaction Level Models
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CODES
2008
IEEE
14 years 11 months ago
Slack analysis in the system design loop
We present a system-level technique to analyze the impact of design optimizations on system-level timing dependencies. This technique enables us to speed up the design cycle by su...
Girish Venkataramani, Seth Copen Goldstein
COMPSAC
2003
IEEE
15 years 3 months ago
A Graph Grammar Approach to Software Architecture Verification and Transformation
Software architecture and design are usually modeled and represented by informal diagrams, such as architecture diagrams and UML diagrams. While these graphic notations are easy t...
Jun Kong, Kang Zhang, Jing Dong, Guang-Lei Song
MONET
2008
90views more  MONET 2008»
14 years 9 months ago
Cognitive Radio Design on an MPSoC Reconfigurable Platform
Cognitive Radio has been proposed as a promising technology to solve today's spectrum scarcity problem by dynamic spectrum access. The MPSoC reconfigurable platform is propose...
Qiwei Zhang, André B. J. Kokkeler, Gerard J...
DAC
2004
ACM
15 years 10 months ago
Abstraction of assembler programs for symbolic worst case execution time analysis
ion of Assembler Programs for Symbolic Worst Case Execution Time Analysis Tobias Schuele Tobias.Schuele@informatik.uni-kl.de Klaus Schneider Klaus.Schneider@informatik.uni-kl.de Re...
Klaus Schneider, Tobias Schüle
VLDB
1998
ACM
134views Database» more  VLDB 1998»
15 years 1 months ago
Secure Buffering in Firm Real-Time Database Systems
The design of secure buffer managers for database systems supporting real-time applications with firm deadlines is studied here. We first identify the design challenges and then p...
Binto George, Jayant R. Haritsa