275 search results - page 37 / 55 » Design for Verification of SystemC Transaction Level Models |
100
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DATE
2005
IEEE
15 years 3 months ago
2005
IEEE
We present a complete top-down design of a low-power multi-channel clock recovery circuit based on gated current-controlled oscillators. The flow includes several tools and method...
ICCD
2008
IEEE
15 years 6 months ago
2008
IEEE
—One of the major design verification challenges in the development of Anton, a massively parallel special-purpose machine for molecular dynamics, was to provide evidence that co...
110
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TCAD
2008
14 years 9 months ago
2008
Manufacturing process variations lead to variability in circuit delay and, if not accounted for, can cause excessive timing yield loss. The familiar traditional approaches to timin...
DATE
2008
IEEE
15 years 4 months ago
2008
IEEE
Continuous and discrete components can be integrated in diverse systems including defense, medical, electronic, communication, and automotive applications. Given the heterogeneity...
DAC
2004
ACM
15 years 10 months ago
2004
ACM
An ever increasing number of dynamic interactive applications are implemented on portable consumer electronics. Designers depend largely on operating systems to map these applicat...