275 search results - page 41 / 55 » Design for Verification of SystemC Transaction Level Models |
172
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DATE
2004
IEEE
15 years 10 months ago
2004
IEEE
Functional verification is widely acknowledged as a major bottleneck in microprocessor design. While early work on specification driven functional test program generation has prop...
176
Voted
INFORMATICALT
2006
15 years 6 months ago
2006
Abstract. This paper presents identity based serial and parallel multisignature schemes using bilinear pairings. Our serial multisignature scheme requires a forced verification at ...
194
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CODES
2004
IEEE
15 years 10 months ago
2004
IEEE
As a result of improvements in process technology, more and more components are being integrated into a single System-on-Chip (SoC) design. Communication between these components ...
177
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VLSID
2001
IEEE
16 years 7 months ago
2001
IEEE
In this paper we describe a hardware design method for memory and register arrays that allows the application of formal equivalence checking for comparing a high-level register tr...
174
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TECS
2008
15 years 6 months ago
2008
straction SUDEEP PASRICHA and NIKIL DUTT University of California, Irvine and MOHAMED BEN-ROMDHANE Newport Media Inc. Currently, system-on-chip (SoC) designs are becoming increasin...