275 search results - page 41 / 55 » Design for Verification of SystemC Transaction Level Models |
DATE
2004
IEEE
15 years 1 months ago
2004
IEEE
Functional verification is widely acknowledged as a major bottleneck in microprocessor design. While early work on specification driven functional test program generation has prop...
INFORMATICALT
2006
14 years 9 months ago
2006
Abstract. This paper presents identity based serial and parallel multisignature schemes using bilinear pairings. Our serial multisignature scheme requires a forced verification at ...
CODES
2004
IEEE
15 years 1 months ago
2004
IEEE
As a result of improvements in process technology, more and more components are being integrated into a single System-on-Chip (SoC) design. Communication between these components ...
VLSID
2001
IEEE
15 years 10 months ago
2001
IEEE
In this paper we describe a hardware design method for memory and register arrays that allows the application of formal equivalence checking for comparing a high-level register tr...
TECS
2008
14 years 9 months ago
2008
straction SUDEEP PASRICHA and NIKIL DUTT University of California, Irvine and MOHAMED BEN-ROMDHANE Newport Media Inc. Currently, system-on-chip (SoC) designs are becoming increasin...