275 search results - page 50 / 55 » Design for Verification of SystemC Transaction Level Models |
AES
2008
Springer
14 years 9 months ago
2008
Springer
This paper presents research that led to the design and implementation of an extensible and scalable software framework for the dynamic 3D visualization of simulated construction ...
104
click to vote
DAC
2004
ACM
15 years 10 months ago
2004
ACM
Parametric representations used for symbolic simulation of circuits usually use BDDs. After a few steps of symbolic simulation, state set representation is converted from one para...
EMSOFT
2008
Springer
14 years 11 months ago
2008
Springer
Relations between models are important for effective automatic validation, for comparing implementations with specifications, and for increased understanding of embedded systems d...
99
Voted
DAC
2003
ACM
15 years 10 months ago
2003
ACM
We present an algorithm that checks behavioral consistency between an ANSI-C program and a circuit given in Verilog using Bounded Model Checking. Both the circuit and the program ...
SIGCOMM
2009
ACM
15 years 4 months ago
2009
ACM
Network management operations are complicated, tedious and error-prone, requiring significant human involvement and expert knowledge. In this paper, we first examine the fundame...