275 search results - page 5 / 55 » Design for Verification of SystemC Transaction Level Models |
59
Voted
ACSD
2005
IEEE
15 years 3 months ago
2005
IEEE
We describe a toolbox for the analysis of Systems-on-achip described in SystemC at the transactional level. The tools are able to extract information from SystemC code, and to bui...
CODES
2008
IEEE
14 years 11 months ago
2008
IEEE
SystemC is widely used for modeling and simulation in hardware/software co-design. Due to the lack of a complete formal semantics, it is not possible to verify SystemC designs. In...
FDL
2004
IEEE
15 years 1 months ago
2004
IEEE
Reconfigurability is becoming an important part of System-on-Chip (SoC) design to cope with the increasing demands for simultaneous flexibility and computational power. Current ha...
SAMOS
2004
Springer
15 years 3 months ago
2004
Springer
The SystemC language plays an increasingly important role in the system-level design domain, facilitating designers to start with modeling and simulating system components and thei...
DATE
2003
IEEE
15 years 3 months ago
2003
IEEE
We propose a new approach to accelerate transaction level verification by raising the productivity of the verification suites including test patterns, protocol checker, and simula...