275 search results - page 8 / 55 » Design for Verification of SystemC Transaction Level Models |
FDL
2005
IEEE
15 years 3 months ago
2005
IEEE
In today’s flows, there is still a gap between system level description and hardware implementation, especially for analog/RF building blocks. SystemC-AMS or co-simulations have...
DATE
2005
IEEE
15 years 3 months ago
2005
IEEE
This paper presents the methodology and the modeling constructs we have developed to capture the real time aspects of RTOS simulation models in a System Level Design Language (SLD...
84
Voted
DATE
2003
IEEE
15 years 3 months ago
2003
IEEE
The design of high performance multimedia systems in a short time force us to use IP's blocks in many designs. However, their correct integration in a design implies more com...
DATE
2005
IEEE
15 years 3 months ago
2005
IEEE
In this paper, we present a SoC design methodology joining the capabilities of UML and SystemC to operate at systemlevel. We present a UML 2.0 profile of the SystemC language expl...
ISVLSI
2006
IEEE
15 years 3 months ago
2006
IEEE
Due to increasing design complexity new methodologies for system modeling have been established in VLSI CAD. The SystemC methodology gains a significant reduction of design cycle...