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» Design for Verification of SystemC Transaction Level Models
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FDL
2007
IEEE
15 years 4 months ago
Modelling Alternatives for Cycle Approximate Bus TLMs
Transaction level models (TLMs) can be constructed at t levels of abstraction, denoted as untimed (UT), cycle-approximate (CX), and cycle accurate (CA) in this paper. The choice o...
Martin Radetzki, Rauf Salimi Khaligh
FDL
2007
IEEE
15 years 4 months ago
An Integrated SystemC Debugging Environment
Since its first release the system level language SystemC had a significant impact on various areas in VLSI-CAD. One remarkable benefit of SystemC lies in the of abstraction le...
Frank Rogin, Christian Genz, Rolf Drechsler, Steff...
DATE
2003
IEEE
119views Hardware» more  DATE 2003»
15 years 3 months ago
IPSIM: SystemC 3.0 Enhancements for Communication Refinement
Refinement is a key methodology for SoC design. The proposed IPSIM design environment, based on a C++ modeling library developed on top of SystemC 3.0, supports an object-oriented...
Marcello Coppola, Stephane Curaba, Miltos D. Gramm...
DAC
2007
ACM
15 years 1 months ago
Verification Methodologies in a TLM-to-RTL Design Flow
SoC based system developments commonly employ ESL design ogies and utilize multiple levels of abstract models to provide feasibility study models for architects and development pl...
Atsushi Kasuya, Tesh Tesfaye
FDL
2006
IEEE
15 years 3 months ago
Layered UML Workload and SystemC Platform Models
Future mobile devices will be based on heterogeneous multiprocessing platforms accommodating several currently stand-alone applications. Increasing complexity of both application ...
Jari Kreku, Yang Qu, Juha-Pekka Soininen, Kari Tie...