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ISCA
2010
IEEE
205views Hardware» more  ISCA 2010»
15 years 3 months ago
The virtual write queue: coordinating DRAM and last-level cache policies
In computer architecture, caches have primarily been viewed as a means to hide memory latency from the CPU. Cache policies have focused on anticipating the CPU’s data needs, and...
Jeffrey Stuecheli, Dimitris Kaseridis, David Daly,...
PLDI
2010
ACM
15 years 3 months ago
Supporting speculative parallelization in the presence of dynamic data structures
The availability of multicore processors has led to significant interest in compiler techniques for speculative parallelization of sequential programs. Isolation of speculative s...
Chen Tian, Min Feng, Rajiv Gupta
RTSS
2002
IEEE
15 years 2 months ago
Improving Quality-of-Control Using Flexible Timing Constraints: Metric and Scheduling Issues
Closed-loop control systems are dynamic systems subject to perturbations. One of the main concerns of the control is to design controllers to correct or limit the deviation that t...
Pau Martí, Josep M. Fuertes, Gerhard Fohler...
SIGMOD
2010
ACM
211views Database» more  SIGMOD 2010»
15 years 2 months ago
Enterprise information extraction: recent developments and open challenges
Information extraction (IE) — the problem of extracting structured information from unstructured text — has become an increasingly important topic in recent years. A SIGMOD 20...
Laura Chiticariu, Yunyao Li, Sriram Raghavan, Fred...
MSWIM
2009
ACM
15 years 2 months ago
Modeling and performance evaluation of transmission control protocol over cognitive radio ad hoc networks
Cognitive Radio (CR) technology constitutes a new paradigm to provide additional spectrum utilization opportunities in wireless ad hoc networks. Recent research in this field has ...
Marco Di Felice, Kaushik Roy Chowdhury, Luciano Bo...
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