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ICPP
2000
IEEE
15 years 1 months ago
A Problem-Specific Fault-Tolerance Mechanism for Asynchronous, Distributed Systems
The idle computers on a local area, campus area, or even wide area network represent a significant computational resource--one that is, however, also unreliable, heterogeneous, an...
Adriana Iamnitchi, Ian T. Foster
DAC
2005
ACM
15 years 11 months ago
A low latency router supporting adaptivity for on-chip interconnects
The increased deployment of System-on-Chip designs has drawn attention to the limitations of on-chip interconnects. As a potential solution to these limitations, Networks-on -Chip...
Jongman Kim, Dongkook Park, Theo Theocharides, Nar...
VLSID
2004
IEEE
170views VLSI» more  VLSID 2004»
15 years 10 months ago
On-chip networks: A scalable, communication-centric embedded system design paradigm
As chip complexity grows, design productivity boost is expected from reuse of large parts and blocks of previous designs with the design effort largely invested into the new parts...
Jörg Henkel, Srimat T. Chakradhar, Wayne Wolf
85
Voted
CCR
2008
91views more  CCR 2008»
14 years 10 months ago
Serial experiments online
Current network protocols must comply with rigid interfaces and rules of behavior to fit into well defined, vertical protocol stacks. It is difficult for network designers to offe...
Juan J. Ramos-Muñoz, Lidia Yamamoto, Christ...
DSD
2007
IEEE
116views Hardware» more  DSD 2007»
15 years 4 months ago
Evaluating the Model Accuracy in Automated Design Space Exploration
Design space exploration is used to shorten the design time of System-on-Chips (SoCs). The models used in the exploration need to be both accurate and fast to simulate. This paper...
Kalle Holma, Mikko Setälä, Erno Salminen...