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» Design in reliability for communication designs
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ASPDAC
2006
ACM
95views Hardware» more  ASPDAC 2006»
15 years 4 months ago
The design and implementation of a low-latency on-chip network
— Many of the issues that will be faced by the designers of multi-billion transistor chips may be alleviated by the presence of a flexible global communication infrastructure. I...
Robert D. Mullins, Andrew West, Simon W. Moore
DAC
2009
ACM
15 years 11 months ago
Statistical reliability analysis under process variation and aging effects
Circuit reliability is affected by various fabrication-time and run-time effects. Fabrication-induced process variation has significant impact on circuit performance and reliabilit...
Yinghai Lu, Li Shang, Hai Zhou, Hengliang Zhu, Fan...
JACIII
2008
75views more  JACIII 2008»
14 years 10 months ago
I3P: A Protocol for Increasing Reliability and Responsiveness in Massively Multiplayer Games
Developing broadband and internet technologies offers possibilities for new ways of minimizing the server bottleneck in online gaming as well as an increase in response and reliab...
Jeremy Kackley, Matthew Gambrell, Jean Gourd
ISCA
2007
IEEE
120views Hardware» more  ISCA 2007»
15 years 4 months ago
Examining ACE analysis reliability estimates using fault-injection
ACE analysis is a technique to provide an early reliability estimate for microprocessors. ACE analysis couples data from performance models with low level design details to identi...
Nicholas J. Wang, Aqeel Mahesri, Sanjay J. Patel
ICITS
2011
14 years 1 months ago
Homogeneous Faults, Colored Edge Graphs, and Cover Free Families
In this paper, we use the concept of colored edge graphs to model homogeneous faults in networks. We then use this model to study the minimum connectivity (and design) requirements...
Yongge Wang, Yvo Desmedt