Many state-of-the-art approaches on fault-tolerant system design make the simplifying assumption that all faults are detected within a certain time interval. However, based on a d...
Jia Huang, Kai Huang, Andreas Raabe, Christian Buc...
In deep submicron VLSI circuits, interconnect reliability due to electromigration and thermal effects is fast becoming a serious design issue particularly for long signal lines. T...
In this study we focus on the specification and assessment of Stochastic Petri net (SPN) models to evaluate the design of an embedded system for reliability and availability. The ...
Frederick T. Sheldon, Stefan Greiner, Matthias Ben...
Due to difficulties in distributing a single global clock signal over increasingly large chip areas, a globally asynchronous, locally synchronous design is considered a promising ...
DRAM is facing severe scalability challenges in sub-45nm technology nodes due to precise charge placement and sensing hurdles in deep-submicron geometries. Resistive memories, suc...
Engin Ipek, Jeremy Condit, Edmund B. Nightingale, ...