5 search results - page 1 / 1 » Design methodology for global resonant H-tree clock distribu... |
70
Voted
ISCAS
2006
IEEE
15 years 3 months ago
2006
IEEE
Abstract—Design guidelines for resonant H-tree clock distribution networks are presented in this paper. A distributed model of a two-level resonant H-tree structure is described,...
GLVLSI
2006
IEEE
15 years 3 months ago
2006
IEEE
A sensitivity analysis of resonant H-tree clock distribution networks is presented in this paper for a TSMC 0.18 μm CMOS technology. The analysis focuses on the effect of the dri...
68
Voted
DAC
1999
ACM
15 years 1 months ago
1999
ACM
In deep submicron technology, IR-drop and clock skew issues become more crucial to the functionality of chip. This paper presents a oorplan-based power and clock distribution meth...
72
Voted
ICCAD
2003
IEEE
15 years 6 months ago
2003
IEEE
— In this paper, we present a high-level power model to estimate the power consumption in semi-global and global interconnects. Such interconnects are used for communications bet...
ACSC
2003
IEEE
15 years 2 months ago
2003
IEEE
Clusters of commodity machines have become a popular way of building cheap high performance parallel computers. Many of these designs rely on standard Ethernet networks as a syste...