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93
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ISQED
2010
IEEE
123views Hardware» more  ISQED 2010»
15 years 1 months ago
Yield-constrained digital circuit sizing via sequential geometric programming
Circuit design under process variation can be formulated mathematically as a robust optimization problem with a yield constraint. Existing methods force designers to either resort...
Yu Ben, Laurent El Ghaoui, Kameshwar Poolla, Costa...
87
Voted
ICCAD
2007
IEEE
139views Hardware» more  ICCAD 2007»
15 years 8 months ago
Remote activation of ICs for piracy prevention and digital right management
— We introduce a remote activation scheme that aims to protect integrated circuits (IC) intellectual property (IP) against piracy. Remote activation enables designers to lock eac...
Yousra Alkabani, Farinaz Koushanfar, Miodrag Potko...
DATE
2009
IEEE
202views Hardware» more  DATE 2009»
15 years 6 months ago
Design as you see FIT: System-level soft error analysis of sequential circuits
Soft errors in combinational and sequential elements of digital circuits are an increasing concern as a result of technology scaling. Several techniques for gate and latch hardeni...
Daniel Holcomb, Wenchao Li, Sanjit A. Seshia
140
Voted
CC
2008
Springer
240views System Software» more  CC 2008»
15 years 1 months ago
Hardware JIT Compilation for Off-the-Shelf Dynamically Reconfigurable FPGAs
JIT compilation is a model of execution which translates at run time critical parts of the program to a low level representation. Typically a JIT compiler produces machine code fro...
Etienne Bergeron, Marc Feeley, Jean-Pierre David
DATE
2003
IEEE
75views Hardware» more  DATE 2003»
15 years 5 months ago
Circuit and Platform Design Challenges in Technologies beyond 90nm
There are already a huge number of problems for silicon designers and it is likely to just get worse. Many of these problems are technical associated with shrinking geometries and...
Bill Grundmann, Rajesh Galivanche, Sandip Kundu