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» Design of Digital Circuits on the Basis of Hardware Template...
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102
Voted
ISPD
2004
ACM
146views Hardware» more  ISPD 2004»
15 years 2 months ago
Power-aware clock tree planning
Modern processors and SoCs require the adoption of poweroriented design styles, due to the implications that power consumption may have on reliability, cost and manufacturability ...
Monica Donno, Enrico Macii, Luca Mazzoni
ICCD
2005
IEEE
221views Hardware» more  ICCD 2005»
15 years 6 months ago
Broadband Impedance Matching for Inductive Interconnect in VLSI Packages
Abstract— Noise induced by impedance discontinuities from VLSI packaging is one of the leading challenges facing system level designers in the next decade. The performance of IC ...
Brock J. LaMeres, Sunil P. Khatri
ICCAD
2003
IEEE
148views Hardware» more  ICCAD 2003»
15 years 6 months ago
Multi.Objective Hypergraph Partitioning Algorithms for Cut and Maximum Subdomain Degree Minimization
In this paper we present a family of multi-objective hypergraph partitioning algorithms based on the multilevel paradigm, which are capable of producing solutions in which both th...
Navaratnasothie Selvakkumaran, George Karypis
DAC
2008
ACM
15 years 10 months ago
Automated hardware-independent scenario identification
Scenario-based design exploits the time-varying execution behavior of applications by dynamically adapting the system on which they run. This is a particularly interesting design ...
Juan Hamers, Lieven Eeckhout
81
Voted
ISPD
2003
ACM
110views Hardware» more  ISPD 2003»
15 years 2 months ago
Explicit gate delay model for timing evaluation
Delay evaluation is always a crucial concern in the VLSI design and it becomes increasingly more critical in the nowadays deep-submicron technology. To obtain an accurate delay va...
Muzhou Shao, Martin D. F. Wong, Huijing Cao, Youxi...