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» Design of Digital Circuits on the Basis of Hardware Template...
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VLSID
1999
IEEE
87views VLSI» more  VLSID 1999»
15 years 3 months ago
Digital Circuit Design for Minimum Transient Energy and a Linear Programming Method
This paper provides a theoretical basis for eliminating or reducing the energy consumption due to transients in a synchronous digital circuit. The transient energy is minimized wh...
Vishwani D. Agrawal, Michael L. Bushnell, Ganapath...
FMCAD
2000
Springer
15 years 3 months ago
B2M: A Semantic Based Tool for BLIF Hardware Descriptions
BLIF is a hardware description language designed for the hierarchical description of sequential circuits. We give a denotational semantics for BLIF-MV, a popular dialect of BLIF, t...
David A. Basin, Stefan Friedrich, Sebastian Mö...
ISMVL
2006
IEEE
99views Hardware» more  ISMVL 2006»
15 years 5 months ago
Signal Processing Algorithms and Multiple-Valued Logic Design Methods
Multiple-valued logic can be viewed as an alternative approach to solving many problems in transmission, storage, and processing of large and even increasing amounts of informatio...
Jaakko Astola, Radomir S. Stankovic
FCCM
2002
IEEE
133views VLSI» more  FCCM 2002»
15 years 4 months ago
Reconfigurable Shape-Adaptive Template Matching Architectures
This paper presents three reconfigurable computing approaches for a Shape-Adaptive Template Matching (SA-TM) method to retrieve arbitrarily shaped objects within images or video f...
Jörn Gause, Peter Y. K. Cheung, Wayne Luk
ARITH
2003
IEEE
15 years 5 months ago
A Low Complexity and a Low Latency Bit Parallel Systolic Multiplier over GF(2m) Using an Optimal Normal Basis of Type II
Using the self duality of an optimal normal basis (ONB) of type II, we present a bit parallel systolic multiplier over GF(2m ) which has a low hardware complexity and a low latenc...
Soonhak Kwon