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» Design of Neuromorphic Hardwares
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CCS
2006
ACM
15 years 5 months ago
TCG inside?: a note on TPM specification compliance
The Trusted Computing Group (TCG) has addressed a new generation of computing platforms employing both supplemental hardware and software with the primary goal to improve the secu...
Ahmad-Reza Sadeghi, Marcel Selhorst, Christian St&...
128
Voted
FPGA
2004
ACM
163views FPGA» more  FPGA 2004»
15 years 5 months ago
Time and area efficient pattern matching on FPGAs
Pattern matching for network security and intrusion detection demands exceptionally high performance. Much work has been done in this field, and yet there is still significant roo...
Zachary K. Baker, Viktor K. Prasanna
142
Voted
EDCC
2006
Springer
15 years 5 months ago
SEU Mitigation Techniques for Microprocessor Control Logic
The importance of fault tolerance at the processor architecture level has been made increasingly important due to rapid advancements in the design and usage of high performance de...
T. S. Ganesh, Viswanathan Subramanian, Arun K. Som...
APCSAC
2001
IEEE
15 years 5 months ago
Exploiting Java Instruction/Thread Level Parallelism with Horizontal Multithreading
Java bytecodes can be executed with the following three methods: a Java interpretor running on a particular machine interprets bytecodes; a Just-In-Time (JIT) compiler translates ...
Kenji Watanabe, Wanming Chu, Yamin Li
147
Voted
ADBIS
1995
Springer
155views Database» more  ADBIS 1995»
15 years 5 months ago
The MaStA I/O Cost Model and its Validation Strategy
Crash recovery in database systems aims to provide an acceptable level of protection from failure at a given engineering cost. A large number of recovery mechanisms are known, and...
S. Scheuerl, Richard C. H. Connor, Ronald Morrison...
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