8345 search results - page 17 / 1669 » Design of Neuromorphic Hardwares |
118
Voted
IWANN
2005
Springer
15 years 7 months ago
2005
Springer
In this paper, a fully functional prototype of an asynchronous 4-to-4 Address Event Representation (AER) mapper is presented. AER is an event driven communication protocol original...
203
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ICCAD
2003
IEEE
15 years 7 months ago
2003
IEEE
While performance, area, and power constraints have been the driving force in designing current communication-enabled embedded systems, post-fabrication and run-time adaptability ...
166
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VLSID
2007
IEEE
16 years 2 months ago
2007
IEEE
We present AHIR, an intermediate representation (IR), that acts as a transition layer between software compilation and hardware synthesis. Such a transition layer is intended to t...
218
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EH
1999
IEEE
1999
IEEE
Evolvable Hardware or Learning Hardware? Induction of State Machines from Temporal Logic Constraints
15 years 6 months ago
Here we advocate an approach to learning hardware based on induction of finite state machines from temporal logic constraints. The method involves training on examples, constraint...
ASPDAC
2004
ACM
15 years 7 months ago
2004
ACM