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» Design of Neuromorphic Hardwares
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ICCD
2007
IEEE
746views Hardware» more  ICCD 2007»
15 years 10 months ago
Hardware design of a Binary Integer Decimal-based floating-point adder
Because of the growing importance of decimal floating-point (DFP) arithmetic, specifications for it are included in the IEEE Draft Standard for Floating-point Arithmetic (IEEE P75...
Charles Tsen, Sonia Gonzalez-Navarro, Michael J. S...
CASES
2006
ACM
15 years 5 months ago
Incremental elaboration for run-time reconfigurable hardware designs
We present a new technique for compiling run-time reconfigurable hardware designs. Run-time reconfigurable embedded systems can deliver promising benefits over implementations in ...
Arran Derbyshire, Tobias Becker, Wayne Luk
150
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ASAP
2006
IEEE
169views Hardware» more  ASAP 2006»
15 years 8 months ago
A Design Methodology for Hardware Acceleration of Adaptive Filter Algorithms in Image Processing
Massively parallel processor array architectures can be used as hardware accelerators for a plenty of dataflow dominant applications. Bilateral filtering is an example of a stat...
Hritam Dutta, Frank Hannig, Jürgen Teich, Ben...
HVC
2007
Springer
103views Hardware» more  HVC 2007»
15 years 8 months ago
Verifying Parametrised Hardware Designs Via Counter Automata
The paper presents a new approach to formal verification of generic (i.e. parametrised) hardware designs specified in VHDL. The proposed approach is based on a translation of suc...
Ales Smrcka, Tomás Vojnar
IWSOC
2003
IEEE
137views Hardware» more  IWSOC 2003»
15 years 7 months ago
Hardware Partitioning Software for Dynamically Reconfigurable SoC Design
CAD tools support is essential in the success of today digital system design methodologies. Unfortunately, most of the classical design tools do not take into account the possibil...
Philippe Brunet, Camel Tanougast, Yves Berviller, ...