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    ITC
    2000
    IEEE
    55views Hardware» more  ITC 2000»
    Low power BIST design by hypergraph partitioning: methodology and architectures
    15 years 6 months ago
    Low power BIST design by hypergraph partitioning: methodology and architectures
    Download  dit.upc.es
    Patrick Girard, Christian Landrault, Loïs Gui...
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    ITC
    2000
    IEEE
    53views Hardware» more  ITC 2000»
    Using on-chip test pattern compression for full scan SoC designs
    15 years 6 months ago
    Using on-chip test pattern compression for full scan SoC designs
    Download  www.lirmm.fr
    Helmut Lang, Jens Pfeiffer, Jeff Maguire
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    ASPDAC
    2000
    ACM
    86views Hardware» more  ASPDAC 2000»
    Low-power design methodology and applications utilizing dual supply voltages
    15 years 6 months ago
    Low-power design methodology and applications utilizing dual supply voltages
    Download  www.cecs.uci.edu
    Kimiyoshi Usami, Mutsunori Igarashi
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    ASPDAC
    2000
    ACM
    97views Hardware» more  ASPDAC 2000»
    MMP: a novel placement algorithm for combined macro block and standard cell layout design
    15 years 6 months ago
    MMP: a novel placement algorithm for combined macro block and standard cell layout design
    Download  www.cecs.uci.edu
    Hong Yu, Xianlong Hong, Yici Cai
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    ISPD
    2000
    ACM
    79views Hardware» more  ISPD 2000»
    Incremental physical design
    15 years 6 months ago
    Incremental physical design
    Download  cadlab.cs.ucla.edu
    Jason Cong, Majid Sarrafzadeh
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