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» Design of Neuromorphic Hardwares
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ERSA
2009
149views Hardware» more  ERSA 2009»
14 years 7 months ago
Hardware-Optimized Ziggurat Algorithm for High-Speed Gaussian Random Number Generators
Many scientific and engineering applications, which are increasingly being ported from software to reconfigurable platforms, require Gaussian-distributed random numbers. Thus, the...
Hassan Edrees, Brian Cheung, McCullen Sandora, Dav...
100
Voted
IMCSIT
2010
14 years 6 months ago
Software and hardware in the loop component for an IEC 61850 Co-Simulation platform
The deployment of IEC61850 standard in the world of substation automation system brings to the use of specific strategies for architecture testing. To validate IEC61850 architectur...
Haffar Mohamad, Thiriet Jean Marc
CASES
2010
ACM
14 years 7 months ago
Hardware trust implications of 3-D integration
3-D circuit-level integration is a chip fabrication technique in which two or more dies are stacked and combined into a single circuit through the use of vertical electroconductiv...
Ted Huffmire, Timothy E. Levin, Michael Bilzor, Cy...
VEE
2012
ACM
187views Virtualization» more  VEE 2012»
13 years 5 months ago
DDGacc: boosting dynamic DDG-based binary optimizations through specialized hardware support
Dynamic Binary Translators (DBT) and Dynamic Binary Optimization (DBO) by software are used widely for several reasons including performance, design simplification and virtualiza...
Demos Pavlou, Enric Gibert, Fernando Latorre, Anto...
BIRTHDAY
2012
Springer
13 years 5 months ago
Operand Folding Hardware Multipliers
This paper describes a new accumulate-and-add multiplication algorithm. The method partitions one of the operands and re-combines the results of computations done with each of the ...
Byungchun Chung, Sandra Marcello, Amir-Pasha Mirba...