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» Design of Synchronous Action Systems
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NOCS
2008
IEEE
16 years 15 days ago
Network Simplicity for Latency Insensitive Cores
In this paper we examine a latency insensitive network composed of very fast and simple circuits that connects SoC cores that are also latency insensitive, de-synchronized, or asy...
Daniel Gebhardt, JunBok You, W. Scott Lee, Kenneth...
150
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DAC
2000
ACM
16 years 7 months ago
Memory aware compilation through accurate timing extraction
Memory delays represent a major bottleneck in embedded systems performance. Newer memory modules exhibiting efficient access modes (e.g., page-, burst-mode) partly alleviate this ...
Peter Grun, Nikil D. Dutt, Alexandru Nicolau
EUROSYS
2007
ACM
16 years 3 months ago
Sprint: a middleware for high-performance transaction processing
Sprint is a middleware infrastructure for high performance and high availability data management. It extends the functionality of a standalone in-memory database (IMDB) server to ...
Lásaro J. Camargos, Fernando Pedone, Marcin...
SAC
2009
ACM
16 years 28 days ago
Variable handling in time-based XML declarative languages
This paper focuses on time-based declarative languages. The use of declarative languages has the advantage of their simplicity and gh-level abstraction, usually requiring few or n...
Luiz Fernando Gomes Soares, Rogério Ferreir...
ADAEUROPE
2009
Springer
16 years 22 days ago
Weak Fairness Semantic Drawbacks in Java Multithreading
With the development of embedded and mobile systems, Java is widely used for application programs and is also considered for implementing systems kernel or application platforms. I...
Claude Kaiser, Jean-François Pradat-Peyre