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79
Voted
DATE
2007
IEEE
15 years 4 months ago
2007
IEEE
This paper proposes an innovative methodology to perform and validate a Failure Mode and Effects Analysis (FMEA) at System-on-Chip (SoC) level. This is done in compliance with the...
HPCA
2000
IEEE
15 years 2 months ago
2000
IEEE
This paper explores area/parallelism tradeo s in the design of distributed shared-memory (DSM) multiprocessors built out of large single-chip computing nodes. In this context, are...
HPDC
2010
IEEE
14 years 10 months ago
2010
IEEE
Massively multicore processors, like, for example, Graphics Processing Units (GPUs), provide, at a comparable price, a one order of magnitude higher peak performance than traditio...
IPPS
2009
IEEE
15 years 4 months ago
2009
IEEE
When investigating the performance of running scientific/ commercial workflows in parallel and distributed systems, we often take into account only the resources allocated to the ...
106
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ISM
2005
IEEE
15 years 3 months ago
2005
IEEE
In this paper we show how an interactive system can be distributed among several peer devices. By taking advantage of the current trend towards ambient intelligent environments, w...