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DAC
1999
ACM
15 years 2 months ago
Power Conscious Fixed Priority Scheduling for Hard Real-Time Systems
Power efficient design of real-time systems based on programmable processors becomes more important as system functionality is increasingly realized through software. This paper ...
Youngsoo Shin, Kiyoung Choi
ICPADS
1994
IEEE
15 years 1 months ago
Delayed Precise Invalidation - A Software Cache Coherence Scheme
: Software cache coherence schemes are very desirable in the design of scalable multiprocessors and massively parallel processors. The authors propose a software cache coherence sc...
T.-S. Hwang, C.-P. Chung
CLUSTER
2001
IEEE
15 years 1 months ago
Parallel Standard Cell Placement on a Cluster of Workstations
In this paper we report experiences on a parallel implementation of a standard cell placement algorithm on a cluster of myrinet connected PCs. The proposed algorithm is based on a...
Faris H. Khundakjie, Patrick H. Madden, Nael B. Ab...
SAC
2008
ACM
14 years 9 months ago
Filtering drowsy instruction cache to achieve better efficiency
Leakage power in cache memories represents a sizable fraction of total power consumption, and many techniques have been proposed to reduce it. As a matter of fact, during a fixed ...
Roberto Giorgi, Paolo Bennati
DAC
1999
ACM
15 years 10 months ago
CAD Directions for High Performance Asynchronous Circuits
This paper describes a novel methodology for high performance asynchronous design based on timed circuits and on CAD support for their synthesis using Relative Timing. This method...
Ken S. Stevens, Shai Rotem, Steven M. Burns, Jordi...