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DAC
2004
ACM
15 years 10 months ago
Dynamic FPGA routing for just-in-time FPGA compilation
Just-in-time (JIT) compilation has previously been used in many applications to enable standard software binaries to execute on different underlying processor architectures. Howev...
Roman L. Lysecky, Frank Vahid, Sheldon X.-D. Tan
COMCOM
1998
102views more  COMCOM 1998»
14 years 9 months ago
Preferred link based delay-constrained least-cost routing in wide area networks
Multimedia applications involving digital audio and/or digital video transmissions require strict QoS constraints (end-to-end delay bound, bandwidth availability, packet loss rate...
R. Sriram, Govindarasu Manimaran, C. Siva Ram Murt...
DATE
2010
IEEE
168views Hardware» more  DATE 2010»
15 years 2 months ago
A new placement algorithm for the mitigation of multiple cell upsets in SRAM-based FPGAs
Modern FPGAs have been designed with advanced integrated circuit techniques that allow high speed and low power performance, joined to reconfiguration capabilities. This makes new...
Luca Sterpone, Niccolò Battezzati
MICRO
2003
IEEE
125views Hardware» more  MICRO 2003»
15 years 3 months ago
WaveScalar
Silicon technology will continue to provide an exponential increase in the availability of raw transistors. Effectively translating this resource into application performance, how...
Steven Swanson, Ken Michelson, Andrew Schwerin, Ma...
TVLSI
2010
14 years 4 months ago
C-Pack: A High-Performance Microprocessor Cache Compression Algorithm
Microprocessor designers have been torn between tight constraints on the amount of on-chip cache memory and the high latency of off-chip memory, such as dynamic random access memor...
Xi Chen, Lei Yang, Robert P. Dick, Li Shang, Haris...