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DAC
2008
ACM
15 years 10 months ago
Miss reduction in embedded processors through dynamic, power-friendly cache design
Today, embedded processors are expected to be able to run complex, algorithm-heavy applications that were originally designed and coded for general-purpose processors. As a result...
Garo Bournoutian, Alex Orailoglu
LCN
2003
IEEE
15 years 2 months ago
A holistic methodology for network processor design
The GigaNetIC project aims to develop high-speed components for networking applications based on massively parallel architectures. A central part of this project is the design, ev...
Olaf Bonorden, Nikolaus Brüls, Uwe Kastens, D...
65
Voted
IPPS
1996
IEEE
15 years 1 months ago
Benefits of Processor Clustering in Designing Large Parallel Systems: When and How?
Advances in multiprocessor interconnect technologyare leading to high performance networks. However, software overheadsassociated with message passing are limiting the processors ...
Debashis Basak, Dhabaleswar K. Panda, Mohammad Ban...
FPL
2004
Springer
128views Hardware» more  FPL 2004»
15 years 3 months ago
Design and Implementation of a CFAR Processor for Target Detection
Real-time performance of adaptive digital signal processing algorithms is required in many applications but it often means a high computational load for many conventional processor...
Cesar Torres-Huitzil, René Cumplido-Parra, ...
DAC
2009
ACM
15 years 10 months ago
Evaluating design trade-offs in customizable processors
The short time-to-market window for embedded systems demands automation of design methodologies for customizable processors. Recent research advances in this direction have mostly...
Unmesh D. Bordoloi, Huynh Phung Huynh, Samarjit Ch...