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IEEEPACT
2009
IEEE
14 years 7 months ago
Algorithmic Skeletons within an Embedded Domain Specific Language for the CELL Processor
Efficiently using the hardware capabilities of the Cell processor, a heterogeneous chip multiprocessor that uses several levels of parallelism to deliver high performance, and bei...
Tarik Saidani, Joel Falcou, Claude Tadonki, Lionel...
P2P
2008
IEEE
176views Communications» more  P2P 2008»
15 years 4 months ago
Towards an Incentive Mechanism for Peer-to-Peer Multimedia Live Streaming Systems
Incentive mechanisms are essential components of peer-topeer systems for file sharing such as BitTorrent, since they enforce peers to share their resources and to participate. Re...
Thomas Silverston, Olivier Fourmaux, Jon Crowcroft
JSA
2010
158views more  JSA 2010»
14 years 4 months ago
Scalable mpNoC for massively parallel systems - Design and implementation on FPGA
The high chip-level integration enables the implementation of large-scale parallel processing architectures with 64 and more processing nodes on a single chip or on an FPGA device...
Mouna Baklouti, Yassine Aydi, Philippe Marquet, Je...
ICPR
2004
IEEE
15 years 10 months ago
From Massively Parallel Image Processors to Fault-Tolerant Nanocomputers
Parallel processors such as SIMD computers have been successfully used in various areas of high performance image and data processing. Due to their characteristics of highly regula...
Jie Han, Pieter Jonker
VLSID
2002
IEEE
174views VLSI» more  VLSID 2002»
15 years 10 months ago
Architecture Implementation Using the Machine Description Language LISA
The development of application specific instruction set processors comprises several design phases: architecture exploration, software tools design, system verification and design...
Oliver Schliebusch, Andreas Hoffmann, Achim Nohl, ...