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ANCS
2006
ACM
15 years 1 months ago
Efficient memory utilization on network processors for deep packet inspection
Deep Packet Inspection (DPI) refers to examining both packet header and payload to look for predefined patterns, which is essential for network security, intrusion detection and c...
Piti Piyachon, Yan Luo
ICS
2010
Tsinghua U.
14 years 8 months ago
Decomposable and responsive power models for multicore processors using performance counters
Abstract—Power modeling based on performance monitoring counters (PMCs) has attracted the interest of many researchers since it become a quick approach to understand and analyse ...
Ramon Bertran, Marc González, Xavier Martor...
CHI
2005
ACM
15 years 10 months ago
StoryGrid: a tangible interface for student expression
StoryGrid is a classroom-based design and presentation system for interactive multimedia posters. Employing the technology base first used in Eden's PitABoard, StoryGrid allo...
Thomas G. Moher, Benjamin Watson, Janet Kim, Claud...
ERSA
2006
197views Hardware» more  ERSA 2006»
14 years 11 months ago
A High Speed, Run Time Reconfigurable Image Acquisition processor for a Missile Approach Warning System
High frame rate video capture and image processing is an important capability for applications in defense and homeland security where incoming missiles must be detected in very sh...
Vinay Sriram, David Kearney
ESTIMEDIA
2009
Springer
14 years 7 months ago
Efficient execution of Kahn process networks on multi-processor systems using protothreads and windowed FIFOs
As single-processor systems are ceasing to scale effectively, multi-processor systems are becoming more and more popular. While there are many challenges of designing multi-process...
Wolfgang Haid, Lars Schor, Kai Huang, Iuliana Baci...