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CHES
2009
Springer
230views Cryptology» more  CHES 2009»
15 years 10 months ago
Designing an ASIP for Cryptographic Pairings over Barreto-Naehrig Curves
Abstract. This paper presents a design-space exploration of an applicationspecific instruction-set processor (ASIP) for the computation of various cryptographic pairings over Barre...
David Kammler, Diandian Zhang, Dominik Auras, Gerd...
ICMCS
2008
IEEE
336views Multimedia» more  ICMCS 2008»
15 years 4 months ago
SIMD optimization of the H.264/SVC decoder with efficient data structure
H.264/scalable video coding (SVC) is a new compression technique that can adapt to various network environments and applications. However, despite its outstanding performance, H.2...
Joohyun Lee, Gwanggil Jeon, Sangjun Park, Taeyoung...
JSA
2010
173views more  JSA 2010»
14 years 4 months ago
Hardware/software support for adaptive work-stealing in on-chip multiprocessor
During the past few years, embedded digital systems have been requested to provide a huge amount of processing power and functionality. A very likely foreseeable step to pursue th...
Quentin L. Meunier, Frédéric P&eacut...
DAC
2005
ACM
15 years 10 months ago
Locality-conscious workload assignment for array-based computations in MPSOC architectures
While the past research discussed several advantages of multiprocessor-system-on-a-chip (MPSOC) architectures from both area utilization and design verification perspectives over ...
Feihui Li, Mahmut T. Kandemir
ASPLOS
2009
ACM
15 years 4 months ago
Architectural implications of nanoscale integrated sensing and computing
This paper explores the architectural implications of integrating computation and molecular probes to form nanoscale sensor processors (nSP). We show how nSPs may enable new compu...
Constantin Pistol, Christopher Dwyer, Alvin R. Leb...