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68
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FPGA
2003
ACM
137views FPGA» more  FPGA 2003»
15 years 2 months ago
Design of FPGA interconnect for multilevel metalization
How does multilevel metalization impact the design of FPGA interconnect? The availability of a growing number of metal layers presents the opportunity to use wiring in the thirddi...
Raphael Rubin, André DeHon
82
Voted
GLOBECOM
2006
IEEE
15 years 3 months ago
Scalable Design of Space-Time Trellis Code with Low Decoding Complexity
—Design of space-time codes that scale with the number of transmit antennas is a difficult problem. In this paper, we introduce a new family of space-time trellis codes (STTC) th...
Kyungmin Kim, Hamid R. Sadjadpour, Rick S. Blum, Y...
74
Voted
HOTI
2008
IEEE
15 years 3 months ago
Low Power Passive Equalizer Design for Computer Memory Links
Several types of low power passive equalizer is proposed and optimized in this work. The equalizer topologies include T-junction, parallel R-C and series R-L structures. These str...
Ling Zhang, Wenjian Yu, Yulei Zhang, Renshen Wang,...
61
Voted
VTC
2007
IEEE
106views Communications» more  VTC 2007»
15 years 3 months ago
Analysis and Design of Dirty Paper Coding by Transformation of Noise
— We design a coding scheme for Costa’s dirty paper coding (DPC) [6] using a channel and a shaping code. We show that by transforming the channel noise distribution the DPC cha...
Young-Seung Lee, Sae-Young Chung
86
Voted
TSP
2010
14 years 4 months ago
Distributed detection of multi-hop information flows with fusion capacity constraints
The problem of detecting multi-hop information flows subject to communication constraints is considered. In a distributed detection scheme, eavesdroppers are deployed near nodes in...
Ameya Agaskar, Ting He, Lang Tong