Wirelength estimation in VLSI layout is fundamental to any pre-detailed routing estimate of timing or routability. In this paper, we develop e cient wirelength estimation techniqu...
Andrew E. Caldwell, Andrew B. Kahng, Stefanus Mant...
Because of the increasing dominance of interconnect issues in advanced IC technology, it is desirable to incorporate global routing into early design stages to get accurate interco...
DIGMAP is a project focused on historical digitized maps that will develop a set of Internet services based on reusable open-source software solutions. The main service will provi...
We present a tool-supported approach to the validation of system-level timing properties in formal models of distributed real-time embedded systems. Our aim is to provide system a...
John S. Fitzgerald, Simon Tjell, Peter Gorm Larsen...
This paper outlines the history of the C++ programming language from the early days of its ISO standardization (1991), through the 1998 ISO standard, to the later stages of the C+...