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CODES
1999
IEEE
15 years 2 months ago
Power estimation for architectural exploration of HW/SW communication on system-level buses
The power consumption due to the HW/SW communication on system-level buses represents one of the major contributions to the overall power budget. A model to estimate the switching...
William Fornaciari, Donatella Sciuto, Cristina Sil...
GECCO
2010
Springer
233views Optimization» more  GECCO 2010»
15 years 2 months ago
Evolutionary-based conflict-free scheduling of collective communications on spidergon NoCs
The Spidergon interconnection network has become popular recently in multiprocessor systems on chips. To the best of our knowledge, algorithms for collective communications (CC) h...
Jirí Jaros, Vaclav Dvorak
DAC
2006
ACM
15 years 10 months ago
Design space exploration using time and resource duality with the ant colony optimization
Design space exploration during high level synthesis is often conducted through ad-hoc probing of the solution space using some scheduling algorithm. This is not only time consumi...
Gang Wang, Wenrui Gong, Brian DeRenzi, Ryan Kastne...
SLIP
2003
ACM
15 years 2 months ago
Error-correction and crosstalk avoidance in DSM busses
Aggressive process scaling and increasing clock rates have made crosstalk noise an important issue in VLSI design. Switching on adjacent wires on long bus lines can increase delay...
Ketan N. Patel, Igor L. Markov
CEC
2009
IEEE
15 years 1 months ago
Search methodologies for efficient planetary site selection
Landing on distant planets is always a challenging task due to the distance and hostile environments found. In the design of autonomous hazard avoidance systems we find the particu...
Luís F. Simões, Tiago C. Pais, Rita ...