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ISCAS
2008
IEEE
103views Hardware» more  ISCAS 2008»
15 years 6 months ago
A low-power monolithically stacked 3D-TCAM
—This paper presents three techniques to reduce the power consumption in ternary content-addressable memories (TCAMs). The first technique is to use newly developed monolithical...
Mingjie Lin, Jianying Luo, Yaling Ma
FCCM
2004
IEEE
141views VLSI» more  FCCM 2004»
15 years 3 months ago
Deep Packet Filter with Dedicated Logic and Read Only Memories
Searching for multiple string patterns in a stream of data is a computationally expensive task. The speed of the search pattern module determines the overall performance of deep p...
Young H. Cho, William H. Mangione-Smith
ISVLSI
2008
IEEE
126views VLSI» more  ISVLSI 2008»
15 years 6 months ago
Standard Cell Like Via-Configurable Logic Block for Structured ASICs
A structured ASIC has some arrays of pre-fabricated yet configurable logic blocks (CLBs) with/without a regular routing fabric. In this paper, we propose a standard cell like via-...
Mei-Chen Li, Hui-Hsiang Tung, Chien-Chung Lai, Run...
CSREAESA
2009
15 years 24 days ago
Embedded Processor Based Fault Injection and SEU Emulation for FPGAs
Two embedded processor based fault injection case studies are presented which are applicable to Field Programmable Gate Arrays (FPGAs) and FPGA cores in configurable System-on-Chip...
Bradley F. Dutton, Mustafa Ali, Charles E. Stroud,...
FPGA
2001
ACM
145views FPGA» more  FPGA 2001»
15 years 4 months ago
Simultaneous logic decomposition with technology mapping in FPGA designs
Conventional technology mapping algorithms for SRAM-based Field Programmable Gate Arrays (FPGAs) are normally carried out on a fixed logic decomposition of a circuit. The impact o...
Gang Chen, Jason Cong