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ITC
2003
IEEE
149views Hardware» more  ITC 2003»
15 years 2 months ago
BIST for Xilinx 4000 and Spartan Series FPGAs: A Case Study
Abstract: We discuss the development of Built-In SelfTest (BIST) configurations that test all of the programmable logic and interconnect resources in the core of Xilinx 4000E, 4000...
Charles E. Stroud, Keshia N. Leach, Thomas A. Slau...
FPL
2000
Springer
130views Hardware» more  FPL 2000»
15 years 1 months ago
Area-Optimized Technology Mapping for Hybrid FPGAs
As integration levels in FPGA devices have increased over the past decade, the structure of programmable logic resources has become more diversified. Recently, Altera Corporation h...
Srini Krishnamoorthy, Sriram Swaminathan, Russell ...
FPGA
2005
ACM
122views FPGA» more  FPGA 2005»
15 years 3 months ago
Power modeling and architecture evaluation for FPGA with novel circuits for Vdd programmability
Vdd-programmable FPGAs have been proposed recently to reduce FPGA power, where Vdd levels can be customized for different circuit elements and unused circuit elements can be powe...
Yan Lin, Fei Li, Lei He
FPGA
2006
ACM
141views FPGA» more  FPGA 2006»
15 years 1 months ago
A reconfigurable architecture for hybrid CMOS/Nanodevice circuits
This report describes a preliminary evaluation of possible performance of an FPGA-like architecture for future hybrid "CMOL" circuits which combine a semiconductor-trans...
Dmitri B. Strukov, Konstantin Likharev
DATE
2002
IEEE
206views Hardware» more  DATE 2002»
15 years 2 months ago
Accurate Area and Delay Estimators for FPGAs
We present an area and delay estimator in the context of a compiler that takes in high level signal and image processing applications described in MATLAB and performs automatic de...
Anshuman Nayak, Malay Haldar, Alok N. Choudhary, P...