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74
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DATE
2010
IEEE
119views Hardware» more  DATE 2010»
15 years 2 months ago
Exploiting local logic structures to optimize multi-core SoC floorplanning
Abstract—We present a throughput-driven partitioning algorithm and a throughput-preserving merging algorithm for the high-level physical synthesis of latency-insensitive (LI) sys...
Cheng-Hong Li, Sampada Sonalkar, Luca P. Carloni
148
Voted
TCAD
2011
14 years 4 months ago
High-Level Synthesis for FPGAs: From Prototyping to Deployment
—Escalating system-on-chip design complexity is the design community to raise the level of abstraction beyond register transfer level. Despite the unsuccessful adoptions of early...
Jason Cong, Bin Liu, Stephen Neuendorffer, Juanjo ...
ISCAS
2003
IEEE
124views Hardware» more  ISCAS 2003»
15 years 2 months ago
An active leakage-injection scheme applied to low-voltage SRAMs
ABSTRACT: An active leakage-injection scheme (ALIS) for lowvoltage (LV) high-density (HD) SRAMs is presented. By means of a feedback loop comprising a servo-amplifier and a commond...
Jader A. De Lima
SGAI
2007
Springer
15 years 3 months ago
Metrics for Mining Multisets
Abstract. We propose a new class of distance measures (metrics) designed for multisets, both of which are a recurrent theme in many data mining applications. One particular instanc...
Walter A. Kosters, Jeroen F. J. Laros
WAE
2001
236views Algorithms» more  WAE 2001»
14 years 11 months ago
Experiences with the Design and Implementation of Space-Efficient Deques
Abstract. A new realization of a space-efficient deque is presented. The data structure is constructed from three singly resizable arrays, each of which is a blockwiseallocated pil...
Jyrki Katajainen, Bjarke Buur Mortensen