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SBCCI
2003
ACM
115views VLSI» more  SBCCI 2003»
15 years 7 months ago
Combining Retiming and Recycling to Optimize the Performance of Synchronous Circuits
Recycling was recently proposed as a system-level design technique to facilitate the building of complex System-on-Chips (SOC) by assembling pre-designed components. Recycling all...
Luca P. Carloni, Alberto L. Sangiovanni-Vincentell...
FCCM
2006
IEEE
162views VLSI» more  FCCM 2006»
15 years 8 months ago
Power Visualization, Analysis, and Optimization Tools for FPGAs
This paper introduces the Low-Power Intelligent Tool Environment (LITE), an object oriented tool set designed for power visualization, analysis, and optimization. These tools lever...
Matthew French, Li Wang, Michael J. Wirthlin
ICDE
2010
IEEE
203views Database» more  ICDE 2010»
15 years 6 months ago
Optimizing ETL workflows for fault-tolerance
Extract-Transform-Load (ETL) processes play an important role in data warehousing. Typically, design work on ETL has focused on performance as the sole metric to make sure that the...
Alkis Simitsis, Kevin Wilkinson, Umeshwar Dayal, M...
ICCAD
2009
IEEE
179views Hardware» more  ICCAD 2009»
15 years 7 days ago
Automatic memory partitioning and scheduling for throughput and power optimization
Hardware acceleration is crucial in modern embedded system design to meet the explosive demands on performance and cost. Selected computation kernels for acceleration are usually ...
Jason Cong, Wei Jiang, Bin Liu, Yi Zou
IEICET
2010
96views more  IEICET 2010»
15 years 1 months ago
An Unsupervised Optimization of Structuring Elements for Noise Removal Using GA
—To recover texture images from impulse noise by the opening operation which is one of morphological operations, an suitable structuring element (SE) has to be estimated. Hithert...
Hiroyuki Okuno, Yoshiko Hanada, Mitsuji Muneyasu, ...