8093 search results - page 130 / 1619 » Design optimization |
135
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GECCO
2007
Springer
15 years 6 months ago
2007
Springer
The multi domain nature of a mechatronic system makes it difficult to model using a single modeling technique over the whole system as varying sets of system variables are require...
122
Voted
FPGA
2008
ACM
15 years 4 months ago
2008
ACM
Logical effort (LE) is a linear technique for modelling the delay of a circuit in a technology independent manner. It offers the potential to simplify delay models for FPGAs and g...
139
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CSREAESA
2004
15 years 3 months ago
2004
: In this paper we focus on the reduction of switching activity in combinational logic circuits. An algorithmic approach using k-map has been proposed which modifies the normal opt...
103
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FLAIRS
2004
15 years 3 months ago
2004
An algorithm is proposed to prune the prototype vectors (prototype selection) used in a nearest neighbor classifier so that a compact classifier can be obtained with similar or ev...
130
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INFOCOM
2012
IEEE
13 years 5 months ago
2012
IEEE
—We study error estimating codes with the goal of establishing better bounds for the theoretical and empirical overhead of such schemes. We explore the idea of using sketch data ...