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DATE
2005
IEEE
154views Hardware» more  DATE 2005»
15 years 8 months ago
A Time Slice Based Scheduler Model for System Level Design
Efficient evaluation of design choices, in terms of selection of algorithms to be implemented as hardware or software, and finding an optimal hw/sw design mix is an important re...
Luciano Lavagno, Claudio Passerone, Vishal Shah, Y...
106
Voted
GECCO
2006
Springer
137views Optimization» more  GECCO 2006»
15 years 6 months ago
Evolutionary design of fault-tolerant analog control for a piezoelectric pipe-crawling robot
In this paper, a genetic algorithm (GA) is used to design faulttolerant analog controllers for a piezoelectric micro-robot. Firstorder and second-order functions are developed to ...
Geoffrey A. Hollinger, David A. Gwaltney
121
Voted
FCCM
2004
IEEE
109views VLSI» more  FCCM 2004»
15 years 6 months ago
Unifying Bit-Width Optimisation for Fixed-Point and Floating-Point Designs
This paper presents a method that offers a uniform treatment for bit-width optimisation of both fixed-point and floating-point designs. Our work utilises automatic differentiation...
Altaf Abdul Gaffar, Oskar Mencer, Wayne Luk, Peter...
121
Voted
GLVLSI
2009
IEEE
154views VLSI» more  GLVLSI 2009»
15 years 9 months ago
Design of a maximum-likelihood detector for cooperative communications in intersymbol interference channels
Recently, cooperative communication has attracted a lot of attention for its potential to increase spatial diversity. However, limited attention has been paid to the physical laye...
Yanjie Peng, Andrew G. Klein, Xinming Huang
99
Voted
ASAP
2007
IEEE
97views Hardware» more  ASAP 2007»
15 years 4 months ago
FPGA-Based Efficient Design Approach for Large-Size Two's Complement Squarers
This paper presents an optimized design approach of two’s complement large-size squarers using embedded multipliers in FPGAs. The realization is based on BaughWooley’s algorit...
Shuli Gao, Noureddine Chabini, Dhamin Al-Khalili, ...