8093 search results - page 14 / 1619 » Design optimization |
DATE
2010
IEEE
15 years 2 months ago
2010
IEEE
— In this paper, we examine the impact of application task mapping on the reliability of MPSoC in the presence of single-event upsets (SEUs). We propose a novel soft erroraware d...
ISQED
2010
IEEE
15 years 4 months ago
2010
IEEE
— Timing exceptions in IC implementation processes, especially timing verification, help reduce pessimism that arises from unnecessary timing constraints by masking non-function...
ASPDAC
2007
ACM
15 years 1 months ago
2007
ACM
Abstract-- This paper proposes a novel power-aware multifrequency wrapper architecture design to achieve at-speed testability. The trade-offs between power dissipation, scan time a...
FPL
2004
Springer
15 years 1 months ago
2004
Springer
In this paper, we develop a unified theory in analyzing optimal switch box design problems, particularly for the unsolved irregular cases, where different pin counts are allowed on...
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DSD
2011
IEEE
13 years 9 months ago
2011
IEEE
—This paper presents an approach for the reliability-aware design optimization of real-time systems on multi-processor platforms. The optimization is based on an extension of wel...