8093 search results - page 173 / 1619 » Design optimization |
146
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FCCM
2007
IEEE
16 years 20 days ago
2007
IEEE
This paper proposes optimizations of the methods and parameters used in both mathematical approximation and hardware design for logarithmic number system (LNS) arithmetic. First, ...
178
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TCAD
2008
15 years 6 months ago
2008
Latency-insensitive protocols allow system-on-chip (SoC) engineers to decouple the design of the computing cores from the design of the intercore communication channels while follo...
159
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ICCAD
2003
IEEE
16 years 3 months ago
2003
IEEE
As the size and complexity of VLSI circuits increase, the need for faster floorplanning algorithms also grows. In this work we introduce Traffic, a new method for creating wire- a...
165
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DATE
2007
IEEE
16 years 20 days ago
2007
IEEE
1 The increasing test data volume needed to test core-based System-on-Chip contributes to long test application times (TAT) and huge automatic test equipment (ATE) memory requireme...
163
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ICCAD
1997
IEEE
15 years 10 months ago
1997
IEEE
This paper presents a unique approach to improve yield given a routed layout. Currently after routing has been completed and compacted, it generally proceeds to verification witho...