The rapidly expanding diversity of technology available at the nanoscale is disrupting the existing transistorcentric microelectronics design paradigm, resulting in nearly decade-l...
This paper presents a highly efficient processor design methodology based on the LISA 2.0 language. Typically the architecture design phase is dominated by an iterative processor ...
Andreas Hoffmann, Frank Fiedler, Achim Nohl, Suren...
With shrinking technology, the timing variation of a digital circuit is becoming the most important factor while designing a functionally reliable circuit. Gate sizing has emerged...
A methodology for constructing circuit-level mismatch models and performing yield optimization is presented for CMOS analog circuits. The methodology combines statistical techniqu...
In most mechanism design settings, optimal general-purpose mechanisms are not known. Thus the automated design of mechanisms tailored to specific instances of a decision scenario...