8093 search results - page 188 / 1619 » Design optimization |
148
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VLDB
1997
ACM
15 years 10 months ago
1997
ACM
Businesses today need to interrelate data stored in diverse systems with differing capabilities, ideally via a single high-level query interface. We present the design of a query ...
142
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ISLPED
2003
ACM
15 years 11 months ago
2003
ACM
Dual-supply voltage design using a clustered voltage scaling (CVS) scheme is an effective approach to reduce chip power. The optimal CVS design relies on a level converter (LC) im...
180
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JCC
2006
15 years 6 months ago
2006
: FASTER is a combinatorial optimization algorithm useful for finding low-energy side-chain configurations in side-chain placement and protein design calculations. We present two s...
250
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ISPD
2012
ACM
14 years 1 months ago
2012
ACM
Gate sizing in VLSI design is a widely-used method for power or area recovery subject to timing constraints. Several previous works have proposed gate sizing heuristics for power ...
201
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VLSID
2002
IEEE
15 years 11 months ago
2002
IEEE
We propose a timing-oriented logic optimization technique called Generalized De Morgan (GDM) transform, that integrates gate resizing, net buffering and De Morgan transformation. ...