462 search results - page 6 / 93 » Design space exploration for 3D architectures |
DAC
2012
ACM
13 years 2 months ago
2012
ACM
In this work, we propose a fast and accurate chip/package thermomechanical stress and reliability co-analysis tool for TSV-based 3D ICs. We also present a design optimization meth...
120
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DAC
2011
ACM
13 years 11 months ago
2011
ACM
In this work, we propose an efficient and accurate full-chip thermomechanical stress and reliability analysis tool and design optimization methodology to alleviate mechanical rel...
DAC
2012
ACM
13 years 2 months ago
2012
ACM
Due to the large geometry of through-silicon-vias (TSVs) and their connections to the power grid, significant current crowding can occur in 3D ICs. Prior works model TSVs and pow...
108
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DAC
2007
ACM
16 years 20 days ago
2007
ACM
Thermal problems and limitations on interlayer via densities are important design constraints on three-dimensional integrated circuits (3D ICs), and need to be considered during g...
93
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DAC
2005
ACM
15 years 1 months ago
2005
ACM
Spatially distributed 3D circuit models are extracted with a segmentto-segment BEM (Boundary Element Method) algorithm for both capacitance and inverse inductance couplings rather...