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» Design space exploration for a coarse grain accelerator
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ARC
2009
Springer
165views Hardware» more  ARC 2009»
14 years 1 months ago
Optimizing the Control Hierarchy of an ECC Coprocessor Design on an FPGA Based SoC Platform
Abstract. Most hardware/software codesigns of Elliptic Curve Cryptography only have one central control unit, typically a 32 bit or 8 bit processor core. With the ability of integr...
Xu Guo, Patrick Schaumont
DATE
2006
IEEE
202views Hardware» more  DATE 2006»
14 years 9 days ago
Automatic systemC design configuration for a faster evaluation of different partitioning alternatives
In this paper we present a methodology that is based on SystemC [1] for rapid prototyping to greatly enhance and accelerate the exploration of complex systems to optimize the syst...
Nico Bannow, Karsten Haug, Wolfgang Rosenstiel
TKDE
1998
122views more  TKDE 1998»
13 years 5 months ago
The Design and Implementation of Seeded Trees: An Efficient Method for Spatial Joins
—Existing methods for spatial joins require pre-existing spatial indices or other precomputation, but such approaches are inefficient and limited in generality. Operand data sets...
Ming-Ling Lo, Chinya V. Ravishankar
DATE
2009
IEEE
81views Hardware» more  DATE 2009»
14 years 1 months ago
ReSim, a trace-driven, reconfigurable ILP processor simulator
— Modern processors are becoming more complex and as features and application size increase, their evaluation is becoming more time-consuming. To date, design space exploration r...
Sotiria Fytraki, Dionisios N. Pnevmatikatos
VLSI
2007
Springer
14 years 11 days ago
Simulation of hybrid computer architectures: simulators, methodologies and recommendations
— In the future, high performance computing systems may consist of multiple multicore processors and reconfigurable logic coprocessors. Industry trends indicate that such coproc...
Pranav Vaidya, Jaehwan John Lee