73 search results - page 6 / 15 » Design space exploration of partially re-configurable embedd... |
108
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SAMOS
2010
Springer
14 years 7 months ago
2010
Springer
—Instruction set simulators (ISS) are vital tools for compiler and processor architecture design space exploration and verification. State-of-the-art simulators using just-in-ti...
SAC
2004
ACM
15 years 2 months ago
2004
ACM
Clustered L0 buffers are an interesting alternative to reduce energy consumption in the instruction memory hierarchy of embedded VLIW processors. Currently, the synthesis of L0 cl...
CHARME
2001
Springer
15 years 2 months ago
2001
Springer
Abstract. We survey the work done so far in the FLaSH project (Functional Languages for Synthesising Hardware) in which the core ideas are (i) using a functional language SAFL to d...
102
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ECRTS
2009
IEEE
14 years 7 months ago
2009
IEEE
This paper explores timing anomalies in WCET analysis. Timing anomalies add to the complexity of WCET analysis and make it hard to apply divide-and-conquer strategies to simplify ...
TCAD
2002
14 years 9 months ago
2002
System-on-a-chip (SOC) platform manufacturers are increasingly adding configurable features that provide power and performance flexibility in order to increase a platform's ap...