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CONCUR
2001
Springer
15 years 6 months ago
Extended Temporal Logic Revisited
A key issue in the design of a model-checking tool is the choice of the formal language with which properties are specified. It is now recognized that a good language should exten...
Orna Kupferman, Nir Piterman, Moshe Y. Vardi
TVLSI
2008
187views more  TVLSI 2008»
15 years 1 months ago
A Design Flow for Architecture Exploration and Implementation of Partially Reconfigurable Processors
During the last years, the growing application complexity, design, and mask costs have compelled embedded system designers to increasingly consider partially reconfigurable applica...
Kingshuk Karuri, Anupam Chattopadhyay, Xiaolin Che...
CVPR
2009
IEEE
16 years 9 months ago
A Revisit of Generative Model for Automatic Image Annotation using Markov Random Fields
Much research effort on Automatic Image Annotation (AIA) has been focused on Generative Model, due to its well formed theory and competitive performance as compared with many we...
Yu Xiang (Fudan University), Xiangdong Zhou (Fudan...
VLSID
2008
IEEE
166views VLSI» more  VLSID 2008»
16 years 2 months ago
Exploring the Processor and ISA Design for Wireless Sensor Network Applications
Power consumption, physical size, and architecture design of sensor node processors have been the focus of sensor network research in the architecture community. What lies at the ...
Shashidhar Mysore, Banit Agrawal, Frederic T. Chon...
ISCAS
2003
IEEE
83views Hardware» more  ISCAS 2003»
15 years 7 months ago
An Integrated Framework of Design Optimization and Space Minimization for DSP applications
This paper presents an Integrated Framework of Design Optimization and Space Minimization (IDOM) for generating the minimum number of functional units with schedule length and mem...
Qingfeng Zhuge, Edwin Hsing-Mean Sha, Chantana Cha...