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DAC
2005
ACM
16 years 20 days ago
Low power network processor design using clock gating
Abstract-- Network processors (NPs) have emerged as successful platforms to providing both high performance and flexibility in building powerful routers. Typical NPs incorporate mu...
Jia Yu, Jun Yang 0002, Laxmi N. Bhuyan, Yan Luo
ICCD
2002
IEEE
115views Hardware» more  ICCD 2002»
15 years 8 months ago
Low-Power, High-Speed CMOS VLSI Design
Ubiquitous computing is a next generation information technology where computers and communications will be scaled further, merged together, and materialized in consumer applicati...
Tadahiro Kuroda
ISCAS
2003
IEEE
147views Hardware» more  ISCAS 2003»
15 years 5 months ago
Parameterized and low power DSP core for embedded systems
Conventional ASIC designs are hard to be customized. Therefore DSP core-based ASIC design has potentially large payoff. This approach not only supports improved performance but al...
Ya-Lan Tsao, Ming Hsuan Tan, Jun-Xian Teng, Shyh-J...
ISQED
2008
IEEE
120views Hardware» more  ISQED 2008»
15 years 6 months ago
Error-Tolerant SRAM Design for Ultra-Low Power Standby Operation
We present an error-tolerant SRAM design optimized for ultra-low standby power. Using SRAM cell optimization techniques, the maximum data retention voltage (DRV) of a 90nm 26kb SR...
Huifang Qin, Animesh Kumar, Kannan Ramchandran, Ja...
IOLTS
2008
IEEE
102views Hardware» more  IOLTS 2008»
15 years 6 months ago
Integrating Scan Design and Soft Error Correction in Low-Power Applications
— Error correcting coding is the dominant technique to achieve acceptable soft-error rates in memory arrays. In many modern circuits, the number of memory elements in the random ...
Michael E. Imhof, Hans-Joachim Wunderlich, Christi...