Sciweavers

5672 search results - page 20 / 1135
» Design techniques for low-power systems
Sort
View
TVLSI
2010
14 years 6 months ago
LOPASS: A Low-Power Architectural Synthesis System for FPGAs With Interconnect Estimation and Optimization
In this paper, we present a low-power architectural synthesis system (LOPASS) for field-programmable gate-array (FPGA) designs with interconnect power estimation and optimization. ...
Deming Chen, Jason Cong, Yiping Fan, Lu Wan
ISQED
2000
IEEE
131views Hardware» more  ISQED 2000»
15 years 4 months ago
Low Power Testing of VLSI Circuits: Problems and Solutions
Power and energy consumption of digital systems may increase significantly during testing. This extra power consumption due to test application may give rise to severe hazards to ...
Patrick Girard
SOSP
2001
ACM
15 years 8 months ago
Real-Time Dynamic Voltage Scaling for Low-Power Embedded Operating Systems
In recent years, there has been a rapid and wide spread of nontraditional computing platforms, especially mobile and portable computing devices. As applications become increasingl...
Padmanabhan Pillai, Kang G. Shin
DAC
2009
ACM
16 years 22 days ago
O-Router:an optical routing framework for low power on-chip silicon nano-photonic integration
In this work, we present a new optical routing framework, O-Router for future low-power on-chip optical interconnect integration utilizing silicon compatible nano-photonic devices...
Duo Ding, Yilin Zhang, Haiyu Huang, Ray T. Chen, D...
ASPDAC
2001
ACM
100views Hardware» more  ASPDAC 2001»
15 years 3 months ago
Low power implementation of a turbo-decoder on programmable architectures
Low Power is an extremely important issue for future mobile radio systems. Channel decoders are essential building blocks of base-band signal processing units in mobile terminal ar...
Frank Gilbert, Alexander Worm, Norbert Wehn