5672 search results - page 22 / 1135 » Design techniques for low-power systems |
DATE
1999
IEEE
15 years 4 months ago
1999
IEEE
Previous work has shown that sizable power reductions can be achieved by shutting down a system's sub-circuits when they are not needed. However, these shutdown techniques fo...
201
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CCECE
2011
IEEE
13 years 11 months ago
2011
IEEE
—In this work the design of a low power 10-bit 100MS/s pipeline ADC is presented. Low power consumption is realized by using an optimum bit per stage resolution and also by apply...
104
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DAC
2005
ACM
16 years 21 days ago
2005
ACM
We propose a system architecture for real-time hardware speech recognition on low-cost, power-constrained devices. The system is intended to support real-time speech-based user in...
DAC
1999
ACM
15 years 4 months ago
1999
ACM
High performance circuit techniques such as domino logic have migrated from the microprocessor world into more mainstream ASIC designs. The problem is that domino logic comes at a...
109
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ICCAD
2002
IEEE
15 years 8 months ago
2002
IEEE
This paper describes an optimization technique able to optimize a complete wireless receiver architecture in a reasonable amount of time. The optimizer alternates between spice le...